Aims to equip learners to build advanced, robust, and reusable testbenches beyond procedural Verilog.
SystemVerilog Fundamentals:
Requires an engineering-level background with expertise in IP design and verification to effectively use SystemVerilog.
Knowledge of object-oriented programming principles is mandatory.
A license for ModelSim/Questa (Siemens EDA), Xcelium (Cadence), or VCS (Synopsys) is required.
Targeted at verification engineers looking to professionalize their verification flow.
Engineer
PowerPoint presentations, mini-projects, and simulations
Assessments at the beginning and end of the course, quizzes …
5 working days before the course start date (if financed by OPCO).
A training certificate complying with the provisions of Article L. 6353-1 paragraph 2 is issued to the trainee.
I subscribe to the training newsletter
