UVM verification methodology awarness

UVM: Concepts and Architecture

• Understanding UVM architecture and components
• Sequences and transactions
• Communication and synchronization
• Stimulus generation and constraints
• Testing and reusability
• Basics of scoreboarding, coverage, and UVM_RAL
• Practical exercises

Requires an engineering-level background with expertise in IP design and verification using SystemVerilog.

Knowledge of object-oriented programming (OOP) principles is mandatory.

A license for ModelSim/Questa (Siemens EDA), Xcelium (Cadence), or VCS (Synopsys) is required.

Targeted at verification engineers aiming to industrialize functional verification, structure object-oriented test environments that are scalable and reusable, and drive closure through coverage.

Engineer

PowerPoint presentations, mini-projects, and simulations

Assessments at the beginning and end of the course, quizzes …

5 working days before the course start date (if financed by OPCO).

A training certificate complying with the provisions of Article L. 6353-1 paragraph 2 is issued to the trainee.